6251-ADA, Adafruit PCM5100 I2S DAC with Line Level Output - 110dB SNR

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US$8.14
6251-ADA
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6251-ADA, Adafruit PCM5100 I2S DAC with Line Level Output - 110dB SNR

The Adafruit PCM5100 I2S DAC with Line Level Output - it's got clean, excellent-quality, stereo audio and does not need any MCLK or I2C configuration. Literally just pipe some I2S audio in and it'll just work.

This breakout makes I2S digital audio easy: all you need to do is power it with 3~5VDC, and provide BCLK (bit clock), WSEL (left/right word select), and DIN (data in). The data lines are 3.3V logic only. By default it's configured for I2S but you can also do Left-Justified by toggling the Format pin. Audio can be 16, 24 or 32-bit wide, the chip will automagically determine the right format from the WSEL / BCLK ratio. No MCLK pin is needed, the chip will auto-generate it internally from the bit clock - or you can provide it on the MCLK input if you want.

Other breakout pads provide: filtering (change from normal to low-latency by pulling high), mute (pull low to quickly set the outputs to ground), and de-emphasis for 44.1khz audio (default is off). The audio outputs are also available on breakout pads if you want to wire directly without using the 3.5mm jack.

Audio output is not AC-coupled because it is centered on ground: you can plug it into anything that is either AC coupled or has the same ground reference. Note that this is a line-level output, it cannot drive headphones - the output is for no less than 1K ohm loads!

Each order comes with one I2S Stereo DAC breakout and some header you can solder on for breadboard usage.

 

Specifications:

  • Market-Leading Low Out-of-Band Noise
  • Selectable Digital-Filter Latency and Performance
  • Accepts 16-, 24-, And 32-Bit Audio Data
  • Sampling Frequency 8kHz to 384kHz
  • PCM Data Formats: I2S, Left-Justified
  • Full Scale Output 2.1VRMS (GND center)
  • Integrated Power-On Reset
  • Automatic Power-Save Mode When LRCK And BCK Are Deactivated.
  • Integrated High-Performance Audio PLL With BCK Reference To Generate SCK Internally
  • 3.3V Failsafe LVCMOS Digital Inputs
  • Hardware Configuration
  • Integrated Negative Charge Pump
  • Internal Pop-Free Control For Sample-Rate Changes Or Clock Halts
  • SNR / Dynamic Range: 110dB
  • THD+N @ - 1dBFS: -90dB
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